xen: arm: configure TCR_EL2 for 40 bit physical address space

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Tim Deegan <tim@xen.org>

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 062645ed7777126cc6a50eff6f9a680d92f4dce2..b8b5902b5830138a73f4b575e41504fac613ed9f 100644 (file)
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -224,12 +224,12 @@ skip_bss:
         msr   mair_el2, x0
 
         /* Set up the HTCR:
-         * PASize -- 4G
+         * PASize -- 40 bits / 1TB
          * Top byte is used
          * PT walks use Outer-Shareable accesses,
          * PT walks are write-back, write-allocate in both cache levels,
          * Full 64-bit address space goes through this table. */
-        ldr   x0, =0x80802500
+        ldr   x0, =0x80822500
         msr   tcr_el2, x0
 
         /* Set up the SCTLR_EL2: